Get Advanced Test Methods for SRAMs: Effective Solutions for PDF

By Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel

ISBN-10: 1441909370

ISBN-13: 9781441909374

ISBN-10: 1441909389

ISBN-13: 9781441909381

Advanced attempt equipment for SRAMs: powerful ideas for Dynamic Fault Detection in Nanoscaled Technologies


Alberto Bosio

Luigi Dilillo

Patrick Girard

Serge Pravossoudovitch

Arnaud Virazel

Modern electronics is determined by nanoscaled applied sciences that current new demanding situations when it comes to checking out and analysis. stories are relatively vulnerable to defects considering the fact that they make the most the know-how limits to get the top density. This ebook is a useful advisor to the trying out and prognosis of the most recent new release of SRAM, some of the most everyday kind of thoughts. Classical tools for trying out reminiscence are designed to address the so-called "static faults", yet those try ideas usually are not adequate for faults which are rising within the most up-to-date Very Deep Sub-Micron (VDSM) applied sciences. those new faults, often called "dynamic faults", aren't coated through classical algorithms and require the devoted try out and analysis recommendations awarded during this book.

  • First booklet to provide entire, cutting-edge assurance of dynamic fault trying out for SRAM memories;
  • Presents content material utilizing a "bottom-up" method, from the examine of reasons of malfunctions as much as the new release of clever try ideas;
  • Includes case stories overlaying all reminiscence elements (core-cells, deal with decoders, write drivers, experience amplifiers, etc.);
  • Proposes an exhaustive research of resistive-open defects in each one reminiscence part and the ensuing dynamic fault modeling.

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Extra info for Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies

Sample text

Ground bounce is a serious problem especially in semiconductor memories, because of the simultaneous switching of a large number of memory core-cells and sense amplifiers. 5 Impact of Technology Scaling 45 the effects of ground bounce and the presence of defects Df2 and Df3 may easily produce the faulty swap of the core-cell. In fact, when ‘1’ is stored, the voltage level of the node at ‘0’ (node SB) can shift down to some 100 mV (Ding and Mazumder 2003) due to ground bounce. Consequently, defective core-cells with defect Df2 or Df3, which present non-detectable malfunction in normal conditions, may swap in the presence of ground bounce and RESs.

During these operations, nodes S and SB are connected to the bit lines BL and BLB by the pass-transistors Mtn3 and Mtn4. The defect involves a delay in the switching ON of these two transistors, reducing the operative time of the read/write operations. The read operation needs a time longer than a write operation to be acted; thus IRFs appear for smaller resistance values than the TFs. – Defect Df6: This fault is at the input of INV2 and involves TFs. It appears for high values of resistance because the defect is placed at the gates of the two transistors of INV2.

At this moment, node S is active low due to the pull-down of inverter INV2 (see Fig. 14), while node SB is floating high because the pull-up of INV2 does not work properly due to the presence of defect Df4. In these conditions, if the leakage current that discharges node SB (especially through Mtn1 and Mtn4) is higher than the current that passes through the faulty pull-up of INV1, the voltage value of node SB decreases from the initial value VDD. When the voltage level of node SB reaches the threshold value of VDD/2, the inverter INV2 switches.

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Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies by Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel

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