Download PDF by Volker Hampel, Grigori Goronzy, Erik Maehle (auth.), Mladen: Architecture of Computing Systems - ARCS 2011: 24th

By Volker Hampel, Grigori Goronzy, Erik Maehle (auth.), Mladen Berekovic, William Fornaciari, Uwe Brinkschulte, Cristina Silvano (eds.)

ISBN-10: 3642191363

ISBN-13: 9783642191367

This publication constitutes the refereed lawsuits of the twenty fourth foreign convention on structure of Computing structures, ARCS 2011, held in Lake Como, Italy, in February 2011. The 22 revised complete papers provided in seven technical classes have been rigorously reviewed and chosen from sixty two submissions. The papers are prepared in topical sections on customization and alertness particular accelerators; multi/many-core architectures; adaptive method architectures; processor architectures; reminiscence architectures optimization; natural and autonomic computing; network-on-chip architectures.

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Additional info for Architecture of Computing Systems - ARCS 2011: 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings

Example text

The Complex Streamed Instructions (CSI) [11] approach also did not make use of any data registers. CSI allows the processing of two-dimensional data streams of arbitrary length, but requires data caches to benefit from data locality. Our approach can use the register file in order to reduce the need for high speed data caches. The Vector Register Windows (VRW) [14] concept allows the grouping of consecutive vector registers in a 2D window. However, one of the dimensions is fixed, contrary to our proposal.

1 Introduction Following Moore’s law, processor frequency doubled every 18 to 24 months until the mid 2000’s. ) and the power consumption caused by the very high frequency, researchers started to look at other strategies to continue to increase system performances. The first solution is to optimize the instruction set for certain application classes. The generalization of the SIMD extensions, which first appeared in the general purpose high performance processors in the early 90’s[1], to all processors including the embedded ones[2] is an evidence of this trend.

Each SM, in turn, contains a set of simple cores that perform in-order processing of the instructions. To achieve high performance, a large number of threads, typically a few tens of thousands, are launched. These threads execute the same operation (instruction) on different sets of data (Single Instruction Multiple Data - SIMD - execution). A block of threads are mapped to and executed on a SM. Furthermore, threads within a block are divided into multiple groups, termed as warp. The memory Experiences with String Matching on the Fermi Architecture 29 Table 1.

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Architecture of Computing Systems - ARCS 2011: 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings by Volker Hampel, Grigori Goronzy, Erik Maehle (auth.), Mladen Berekovic, William Fornaciari, Uwe Brinkschulte, Cristina Silvano (eds.)


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