By R. N. Ibbett, N. P. Topham (auth.)
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Extra info for Architecture of High Performance Computers: Volume I Uniprocessors and vector processors
However, the use of pipelining may often be reflected in the order code of a high performance machine, as we shall see in the following section. Consider an arbitrary computing structure for evaluating a function F, on a stream of input values XI ... Xn, to produce a stream of output values F(xt) ... F(xn)· The performance of this computing structure can be characterised firstly in terms of its latency, and secondly in terms of its throughput. The latency is defined as the delay between supplying input value Xi and receiving at the output of F the value F(xi)· The throughput is defined simply as the rate at which output values are produced by F.
The address path contains 27 bits (including 3 byte-parity bits and one bit which distinguishes user and system addresses). The control field contains some information which is copied directly through the OR gate from the Sending Unit to the Receiving Unit, some information which is copied through the OR gate and is also used by the Exchange controllogic, and some information (the Unit Number) which is modified by the controllogic before being sent to the Receiving Unit. In all, 14 control digits pass between units via the Exchange, making the total width of the OR gate 113 bits, and some additional control signals pass between the Exchange control logic and each of the units.
1 The Exchange In order to provide a completely general and Hexihle interconnection scheme, allowing for data transfers between all these various stores and processors, an Ezchange was developed as part of the MU5 project [LTE77 ,MI79]. , Fixed-head Disc Store PDP- 11/10 MU5 Processor Local Store 1905E Processor and Store Mass Store Figure 9. 7 The MUS Exchange system at the star point of the interconnections. This configuration involves only a very short common path for transfers between the various units, allowing a much higher data rate than would be possible with a distributed highway or bus system.
Architecture of High Performance Computers: Volume I Uniprocessors and vector processors by R. N. Ibbett, N. P. Topham (auth.)