By Hideyuki Matsumura
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Additional info for Commutative Algebra, 2nd ed. (Mathematics Lecture Note Series, 56)
This latter fact can be seen best from an example. It follows from Eq. 67 that N = 9m is a reasonable choice if the actual information rate is not to be substantially less than the nominal rate R = 1/2. period, N + m, is then 10m time units. The resynchronization For J = 10, we have m = thus the resynchronization period is 5110 time units. 2 J- 1 - 1 = 511 and On the other hand, m E = 56 for this code, and hence if nA and nE were equal (which would imply m = 27) the resynchronization period would be only 270 time units.
B. (-R)nA-Stage Encoder A second circuit that performs the operations of Eqs. 28 and 29 is shown in Fig. 6. This circuit has a sequences, shift-register and thus contains a of m stages for each of the n total of m(no-ko) = (-R)(nA-no), (l-R)nA, stages of shift register. encoder. chain or - k parity approximately We shall refer to this circuit as the (l-R)nA-stage The adders in this circuit are placed between stages of the shift-register chains, and hence no adder has more than k + 1 inputs. This can be an important T( 1) i(1) I(ko ) ) D DELAY IONE UNIT Fig.
EACH STAGE OF SHIFT REGISTER HAS DELAY /n TIME UNITS. T (2) 11- ~~~~~EIlYMUIV CAD When it is desired -/ (n ) Fig. 7. Commutating circuit. to transmit these symbols over a single communication channel, they must be serialized to occur at the rate of one symbol every 1/n o time units. This symbol interlacing can be accomplished by a commutating circuit such as the one shown in Fig. 7, which consists principally of a sampling circuit and a shift register of no - 1 stages. d. Remarks on Encoding Circuits The RnA-stage encoder described above is essentially the same as the canonic-form encoder developed by Wozencraft and Reiffen.
Commutative Algebra, 2nd ed. (Mathematics Lecture Note Series, 56) by Hideyuki Matsumura